1. Technical Field
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method for testing a device under test.
2. Related Art
Generally, as a test apparatus that tests a device under test such as a semiconductor memory, and apparatus has been known, which has a tuning generator, a pattern generator, a waveform shaper, a logic comparator, a fail analysis memory and a pattern memory.
The timing generator generates a reference clock to regulate the operation of the test apparatus. The pattern generator generates an address signal, a data signal and a control signal provided to the device under test. The wave form shaper generates a test signal based on those signals and provides the same to the device under test. The pattern memory stores therein a prepared data signal and expected value signal. The waveform shaper may generate a test signal based on the data signal stored in the pattern memory. The logic comparator compares an output signal from the device under test with the expected value signal and generates fail data indicative of pass/fail. The fail data is stored in the fail analysis memory.
Here, any related patent document is not currently found, so that the description is omitted.